The use of a thin pointed tip to form ultra-fine metal lines have found wide application in VLSI semiconductor integrated circuit (IC) chips.
Conventional methods have been used thus far to form patterns of conductive material on a substrate in connection with the fabrication or repair of semiconductor IC chips. Indeed, it is often necessary to form conductive patterns with superior resolution on a semiconductor structure during the various phases of the chip fabrication. Such patterns provide the necessary contacts, electrodes, and conductors (or lines) that are required to meet the various connection/interconnection needs. Conductive materials include doped polysilicon, low melting point metals such as aluminum (Al), metal alloys such as aluminum-silicon (Al-Si), gold-silicon (Au-Si), and refractory metals such as tungsten (W), tantalum (Ta), and chromium (Cr). However, low melting point metals and metal alloys are by far, the most ubiquitous materials used throughout the semiconductor industry. typical method of forming metal patterns is to combine lithography and deposition techniques. E-beam evaporation or sputtering deposition and lift-off lithography are the standard techniques used to date. Typically, a thick photoresist layer is first formed onto a semiconductor structure. The resist is then exposed using a photomask. This exposure serves to trace a predetermined pattern in the resist inducing localized chemical reactions in the exposed regions. The resist layer is then developed in a suitable solvent and the exposed regions (in case of a positive resist) are removed. Next, a metal layer is blanket sputtered onto the structure and the remaining portions of the resist layer are removed, leaving the desired complementary metal pattern on the surface of the structure.
The above described method is extensively used in the industrial production of semiconductor IC chips. However, it has some significant limitations for customizing and repairing chips. The conventional method described above, however, is still used in customizing (or personalizing) CMOS gate arrays. For instance, eight out of the twelve photomasks of a typical CMOS process are generic. However, there is a strong demand for fast turn-around of prototypes, small production volumes and significant engineering support in the chip design and evaluation stages, all of which put pressure on gate array manufacturers. Obviously, lithography is hard pressed to cope with the short delays demanded by the marketplace to produce a customized chip or to repair a defective chip. As a result, the above described method cannot be used for instant customizing of ASICs (Application Specific Integrated Circuits) or for chip repair.
Other conventional methods have been successfully used to form patterns of an opaque material in connection with the manufacture of photomasks, but they usually use other lithographic techniques. By way of example, according to a typical fabricating photomask process, a metal (usually chromium) coated transparent glass plate is first covered with a radiation sensitive resist layer. The resist is exposed using a well collimated E-beam and developed. The remaining patterned resist layer acts as a protective layer to the underlying metal coating. In turn, the unprotected metal is etched up to the glass plate. Finally, the remaining resist layer is removed, leaving opaque zones of metal on the glass plate surface. As known to those skilled in the art, photomasks are currently used in the lithographic steps in the course of IC chip manufacture. As far as the fabrication of photomasks is concerned, this lithographic process tends to develop two groups of defects: unwanted portions are left unremoved (so-called black-spot defects) and portions needed are unintentionally etched away (so-called clear or white-spots defects). This method is extensively used in the industrial production of photomasks, but it is clearly not applicable for repair purposes. Using an additional lithographic step to repair a defective mask by performing localized metal deposition thereon makes little or no sense, and more often than not, a new mask is produced.
In summary, lithographic based methods are well adapted to mass producing semiconductor IC chips or photomasks, but are not suited for applications involving small volume production of IC chips, customizing and repair, and mask repair. In addition, lithography has an inherent high capital and operating cost, due to the sophisticated E-beam or photoaligner apparatus that are required to trace a pattern. As a result, alternate methods eliminating lithographic steps during prototyping and engineering have been sought to improve flexibility and save time and expense.
Two recent techniques, known under the name of Focused Ion Beam (FIB) and its variant Focused Ion Beam-Chemical Vapor Deposition (FIB-CVD), obviate most of the drawbacks of above the conventional lithographic processes described. In particular, they are adaptable to the ablation of metal fine lines and to the deposition of metal fine lines, respectively. Consequently, they have found a wide application in various fields of the semiconductor technology, particularly, in the repair of IC chips and masks as well as other related fields, such as process monitoring, defect/failure analysis, device evaluation, sample preparation for microscopy and micro-analysis, and the like. To date, the FIB-CVD is considered the most promising deposition technique, and it is on the verge of significant and rapid advances in the semiconductor industry.
In a standard configuration adapted to metal deposition, a FIB-CVD station is housed within a column-shaped vacuum chamber that includes an X-Y stage capable of controlled movements in the X-Y directions of an horizontal plane. The column encloses a high brightness liquid metal ion source which consists of a sharp needle wetted by a film of the metal, typically gallium (Ga) in its molten state. The molten metal travels by capillary action to the needle of the ion source where it is ionized. An extraction electrode having a difference voltage potential with the ion source extracts the ion beam from the source. There is produced a beam of charged particles, i.e. ions, that appears to emanate from a point. A E.times.B mass separator can be used to select only the desired ion species and deflect the undesired species out of the beam (as for instance, when metal alloy is used). A series of lenses is placed on the path of the ion beam to provide focus. Next, a beam deflector is used to scan the beam over the substrate. The substrate which forms the target for the FIB is generally placed on top of a heating element affixed on the X-Y stage. A thermo-couple sensor senses the substrate temperature, thereby providing control to the heating element. The substrate is heated to a temperature sufficiently high to support growth of the desired material. The compound which includes the material to be deposited on the substrate is held in a gaseous state within a reservoir. A gaseous organometallic compound such as tungsten carbonyl is typically used as a working gas. A valve controls the flow of the working gas from the reservoir through a nozzle which terminates in close proximity of the substrate, and directs a flow of gas onto the desired portion thereof. A few atomic layers of the working gas are adsorbed by the substrate surface.
The focused ion beam generated by the liquid metal ion source is projected onto the substrate and scanned thereon by the beam deflector so that the working gas is decomposed. The tungsten film is only formed in an area where the ion beam impinges on the gas. Metal fine lines are formed continuously. The focused ion beam is scanned along a predetermined locus, corresponding to a desired circuit connection line (preferably in multiple scans) to grow the metal until the desired thickness is obtained. This is clearly a lengthy process, and since the ion beam intensity can only be increased to a limited extent, it is rather difficult to trace relatively long lines, e.g., 1 mm, unless one is willing to accept an appreciable loss in terms of resolution. The secondary electrons emitted from the surface of the substrate are detected, amplified and processed for final display on an appropriate display as a high resolution SIM (Scanning Ion Microscope) image. Since a control unit drives the X-Y stage, it is possible to observe the SIM image of any desired portion of the substrate--a significant advantage for chip or mask repair.
The FIB-CVD station previously described is particularly well suited to perform additive processes, such as deposition of metals. However, it suffices not to use the working gas to transform the station into an equipment that is adapted for subtractive operations, such as etching (reverse sputtering), hole drilling, wire cutting, etc. As a result, the FIB and FIB-CVD techniques can lead to various and interesting applications. By way of example, although the FIB-CVD technique has limited use in the manufacture of IC chips to form electrical connections (wherein active and passive devices have been previously formed by appropriate lithography and implantation steps), it is widely used for repairing such chips. If there is an open in a metal interconnect line that was previously deposited (as a result of a manufacturing defect), the line can be repaired by scanning the open area to deposit new metal and fill the open as described above.
According to the FIB-CVD technique, no limitations exist in the nature of metals to be deposited. For instance, refractory metals, including tungsten, which have a high melting point temperature (of about 3370.degree. C.), are easily deposited on an insulating or a silicon substrate, when using metal carbonyl compounds. However, deposition of such refractory metals is more difficult when GaAs is the semiconductor material, because GaAs is not easily oxidized and metallized. This disadvantage has severely hampered the development of this technology to this date. For example, refractory metal gate electrodes are currently applied to GaAs MESFET devices by sputtering and E-beam evaporation. In both of these processes, damage can occur to the GaAs surface. Sputtering causes impact damage, and E-beam evaporation results in dissociation of GaAs. The preferred method of depositing refractory metals, is a variant of the FIB-CVD technique described above, the so-called photodeposition. As disclosed, for instance, in U.S. Pat. No. 4,451,503 assigned to IBM, photodeposition uses ultraviolet radiation of wavelengths less than 200 nm to photodecompose the gaseous metal carbonyl compound in the vicinity of the GaAs wafer.
For similar reasons, the FIB/FIB-CVD techniques are not well adapted to the manufacture of masks, to form opaque chromium patterns on a glass plate. They have found wider applications in repairing masks, either by depositing new metal on white spot defects that develop in the mask pattern or by ablation of undesired metal portions thereof. Again, in this instance, the SIM image is helpful in pinpointing the exact location of the mask defects to be repaired. Moreover, as mentioned above, it is rather simple to transform the FIB-CVD station into a FIB station adapted to eliminate by ablation the undesired shorts at the surface of the IC chips.
In summary, the FIB/FIB-CVD techniques have numerous applications, including the in-situ formation of metal patterns to be used as circuit connections during the repair or personalization of an IC chip, as well as for the formation of additional opaque patterns during the repair of photomasks. Unfortunately, in particular, the FIB-CVD pattern forming process has some significant drawbacks, as will be explained hereinafter.
In order to obtain good resolution, a low ion beam intensity is required, which in turn implies a ion beam having a very small size diameter size, e.g. 30-40 nm. To create a 2 .mu.m.times.1 .mu.m conductor thus requires multiple scans. The requirement of a relatively high ion dose and an ion beam that must be left on the substrate during the entire deposition process, multiple scans of the line to be deposited significantly slow down the speed at which lines are written. Furthermore, the rate of line (or pattern) build-up to a desired thickness is very low.
Since a chemical deposition is used during the manufacturing process, the resulting resolution is naturally poor. Any attempt to raise the build-up rate mentioned above requires increasing the ion beam intensity, thereby causing the ion beam to become unfocused. This, in turn, results in spreading away the sputtered material excessively.
High resistivity conductors can also be obtained. Impurities, typically, carbon and gallium atoms, are implanted during the pattern formation. When ultra-fine lines are required, the impurity level of the deposited lines may be high, i.e., in excess of 25%, thereby resulting in a sheet resistivity which is much higher than desired. As a result, for the reasons stated, the FIB-CVD technique is limited to the deposition of relatively short lines. Long lines are too resistive and also require too much time.
Organometallic products, such as tungsten carbonyl W(CO)G, molybdenum carbonyl Mo(CO)G, chromium carbonyl (Cr(CO)G, and the like, are extensively used in FIB-CVD but can lead to the formation of dangerous and toxic compounds.
A conventional FIB-CVD station is relatively complicated and expensive and has a high operating cost. It further requires operating in a vacuum environment. Generally, the FIB-CVD station is placed in the vacuum chamber of a scanning electron microscope (SEM).
The FIB-CVD process requires relatively high dosage, in the order of 10.sup.17 ions/cm.sup.2 or greater to deposit patterns or lines that are only a few hundred nanometers thick. The use of such high dosage can result in damage of the wafer surface.
The deposition step requires high temperatures (e.g., 300.degree. C.) to heat the substrate. Should the substrate be a semiconductor wafer, the presence of elevated temperature can result in detrimental phenomenon within the devices integrated therein which could alter the electrical characteristics of the device.
High aspect ratios are achieved with the FIB-CVD technique. A common problem is attributable to the sharp step of conductors that are formed, while in most instances, conductors having tapered edges would have been preferred to avoid the step coverage effect with its well known reliability problems. Thus, although ion beams can be focused to below a micron in diameter and thus have the potential for submicron resolution, a practical way to integrate rapid and efficient metal line deposition into an IC chip manufacture and repair process has not been found thus far. As a result, there still remains the pressing need for a new technique that includes a maximum of advantages of the FIC-CVD deposition technique (possibly by introducing functions not performed by the same), while retaining only a minimum of its disadvantages. Moreover, it should also be adapted to provide some of the subtractive features of the FIB technique. Finally, it would be highly desirable to have this technique adapted to the fabrication of IC chips, so that a mask free fabrication of IC chips with no lithography steps could be envisioned. This technique should also be adaptable to customizing and repairing IC chips and masks, as presently FIB-CVD and FIB techniques are capable of achieving.
Accordingly, it is a primary object of the present invention to provide a method and apparatus for depositing materials of either a conductive and non conductive type on a variety of substrates.
It is another object to provide a method and apparatus for the direct writing of a desired conductive pattern on a substrate having either a regular or irregular surface.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate to form electrical connections at relatively high speed.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate to form electrical connections having precise dimensions.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate to form electrical connections with a resistivity equivalent to the bulk metal.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate to form electrical connection lines of any desired length and width.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate that does not use toxic compounds.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate that requires a relatively inexpensive equipment with a low operating cost.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate that is capable to fill via-holes formed in the substrate.
It is still another object to provide a method and apparatus for depositing a metal pattern on a substrate without damaging the surface of the substrate.
It is still another object to provide a method and apparatus for depositing a metal pattern on a substrate that can be normally performed at room temperature.
It is still another object to provide a method and apparatus for depositing a metal pattern on an insulating substrate, whose lines have tapered edges and rounded corners for improved reliability.
It is still another further object to provide a method and apparatus for depositing a pattern of a refractory metal on a GaAs substrate.
It is still another further object to provide a method and apparatus normally constructed for depositing conductive and non conductive materials on a substrate that can be easily adapted to a subtractive process, such as scribing and electroerosion.
It is still another further object to provide a method and apparatus for depositing successive metal and insulator patterns on a substrate that could lead to a totally mask-free fabrication of IC chips.
It is still another further object to provide a method and apparatus for depositing a metal pattern on a substrate that is adapted to the personalization and repair of IC chips and photomasks.
These and other objects will be accomplished by the method and apparatus of the present invention by directly writing a desired pattern of a given material on a substrate. It is based on the use of a pen or writing head, preferably consisting of a refractory tip wetted in material in a molten state. The tip is formed by a small wire, typically of refractory metal such as tungsten, that has been electrolytically sharpened and roughened. The tip is attached, preferably by micro welding, to the top of a heater, which typically consists of a V-shaped piece of the same tungsten wire. Each end of the V-shaped heater is welded to a pin that emerges from an insulating base support, e.g., a 3-lead TO-5 package, with three pins partially casted therein. The pen is incorporated into an apparatus adapted for direct writing. The tip is attached to a supporting device, preferably adapted to move along the Z-axis, while the substrate moves on an X-Y stage, for X, Y, and Z relative movements therebetween. The two pins of the pen are connected to a power supply to resistively heat the heater. When the welding point of the tip/heater assembly reaches the melting point of the material to be deposited, it is dipped in a crucible containing material in the molten state. The welding point nucleates a minute drop of liquid material and forms a spatial reservoir in the absence of any container. A thin film of the liquid material flows from the reservoir and wets the tip surface. Finally, the wetted tip is gently brought into contact with the substrate and deposition of the material takes place. Physical contact between the tip apex and the substrate surface is not required, which helps limit the wear of the tip. Preferably, the tip/heater assembly is vibrated to facilitate deposition of the material. Alternate configurations of the tip may be used to create different patterns. For instance, ultra-fine lines of metal can be formed to define the electrical connections of an IC chip, or larger zones of opaque material in the repair of a mask.
In essence, the deposition method of the present invention consists in the direct writing of a material on a substrate using a tip wetted in the material in a molten state. These materials can either be of a conductive type including standard metals (Al), metal alloys (Al-Si, Au-Si, . . . ), or refractory metals (Cr, Ta, . . . ) or of a nonconductive type, such as organic or non-organic insulators. The substrate may be selected from a variety of supports and may encompass either a planar or non-planar surface. Moreover, with the method and apparatus of the present invention, a mask free manufacture of semiconductor IC chips, and, particularly, of the III-V type, is henceforth possible. The deposition method of the present invention has numerous advantages and applications not only in the semiconductor technology field but in other fields as well.